The present invention relates to a semiconductor device having a trench-isolated structure and, more particularly, to a method of reducing the capacitance between the wiring and substrate of the semiconductor device.
As higher-density and increasingly miniaturized semiconductor devices have been implemented in recent years, repeated attempts have been made to substitute a trench isolation technique for a LOCOS technique which is most prevalently used to form isolation for providing insulation between individual elements of the semiconductor devices. In accordance with the trench isolation technique, an insulating material is filled in a trench formed in a semiconductor substrate to form isolation.
Since planarization of a surface of a semiconductor substrate including the insulating material filled in the trench is important to the trench isolation technique, chemical mechanical polishing (CMP) has been used as a planarizing technique which achieves excellent in-plane uniformity free from pattern dependence. In the case where the trench occupies a large area in a CMP process for planarization, the provision of dummy island semiconductor portions has been proposed to avoid trouble resulting from so-called pattern dependence, which causes polishing properties to vary depending on the area of a region to be planarized. In other words, the trench is divided into a plurality of narrow trenches so that the surface of the semiconductor substrate is exposed between the individual trenches to form the dummy semiconductor portions which do not serve as active regions.
FIG. 19 shows an example of the conventional trench-isolated semiconductor device having the dummy island semiconductor portions.
As shown in FIG. 19, an active region 6 of a P-type silicon substrate 1 is formed with: a gate oxide film 2; a gate electrode 4 made of a polysilicon film; and source/drain regions 5 into which an impurity has been introduced. An isolation region 7 surrounding the active region 6 is formed with a plurality of trench portions 8 each filled with a silicon oxide film. Between the individual trench portions 8, there are provided semiconductor portions 9 having top surfaces at the same level as the top surfaces of the trench portions 8. On the trench portions 8 also, there is provided a polysilicon wire 10 formed simultaneously with the gate oxide film 2 and the gate electrode 4 of an element. An interlayer insulating film 12 is deposited over the entire surface of the substrate, followed by a metal wire 13 provided thereon.
In this case, if the trench portions have such large widths as shown in FIG. 21(b), a silicon oxide film filled in each of the trench portions is polished during the CMP process for planarizing the whole substrate so that the surface thereof is depressed due to pattern dependence, which leads to the trouble of degraded planarity or the like. The isolation structure as shown in FIG. 19 has been proposed to prevent such trouble resulting from pattern dependence.
FIGS. 20(a) to 20(g) are cross-sectional views illustrating a process of manufacturing the conventional trench-isolated semiconductor device having an NMOS transistor.
In the step shown in FIG. 20(a), a thin silicon oxide film 21 having a thickness of 10 nm and a silicon nitride film 22 are formed sequentially on the P-type silicon substrate 1.
In the step shown in FIG. 20(b), a plurality of trenches 14 each having a given width are formed in the silicon substrate 1. However, the trenches 14 include: trenches 14a formed to surround the active region 6 to be formed with the element; trenches 14b formed in the isolation region 7 separated from the active region 6 by the trenches 14a to eliminate pattern dependence from planarity obtained at the completion of the manufacturing process; and trenches 14c for forming the polysilicon wires. In the isolation region 7 also, the semiconductor portions 9 have been provided to form at least one projecting portion surrounded by the trenches 14. The semiconductor portions 9 may be considered as dummy active regions which do not function as active regions.
In the step shown in FIG. 20(c), a silicon oxide film 23 is deposited over the entire surface of the substrate to fill in the trenches 14.
In the step shown in FIG. 20(d), the silicon oxide film 23 is polished by a CMP method. Subsequently, the silicon nitride film 22 and the silicon oxide film 21 are removed selectively to form the plurality of buried trench portions 8 each filled with the silicon oxide film and having a planarized surface. The buried trench portions 8 include: buried trench portions 8a functioning as isolation; buried trench portions 8b forming the dummy semiconductor portions 9; and buried trench portions 8c for providing insulation between the polysilicon wires and the silicon substrate.
In the step shown in FIG. 20(e), there are formed the gate oxide film 2, the gate electrode 4 having sidewalls 24 on the side faces thereof, and the polysilicon wire 10 by using a known technique. The gate electrode 4 and the polysilicon wire 10 are formed simultaneously.
In the step shown in FIG. 20(f), arsenic ions 25 are implanted into the active region 6 of the NMOSFET region by using a resist mask Rem covering the PMOSFET region and the isolation region to form the source/drain regions 5. The NMOSFET is formed by the foregoing process steps.
In the step shown in FIG. 20(g), the silicon oxide film is deposited to form the interlayer insulating film 12, followed by the metal wire 13 formed thereon.
In the foregoing step shown in FIG. 20(f), ions of such an impurity as phosphorus or arsenic have been implanted into the gate electrode 4 and source/drain regions 5 of the active region 6 in the step shown in FIG. 20(f). However, impurity ions are not implanted in principle in the region other than the active region 6, though they may be introduced slightly extensively into the periphery of the isolation region in considerations of mask displacement. Hence, impurity ions are not implanted in the dummy semiconductor portions 9 between the individual trench portions 8.
A description will be given to the wiring-to-substrate capacitance of the trench-isolated semiconductor device having the small trench portions 8 which are discretely located and the dummy semiconductor portions 9 as shown in FIG. 19 and in a semiconductor device having a wide isolating/insulating film such as a LOCOS film. FIG. 21(a) is a cross-sectional view for illustrating, by way of example, the wiring-to-substrate capacitance in the isolation region 7 having the dummy semiconductor portions 9. FIG. 21(b) is a cross-sectional view for illustrating the wiring-to-substrate capacitance of the semiconductor device having a LOCOS isolation film 100 and no dummy semiconductor portion. It is assumed here that impurity ions have not been implanted in the isolation region 7 during the implantation of ions into the source/drain regions and that the area occupied by the whole isolation region 7 is equal in each of the two semiconductor devices.
In the semiconductor device shown in FIG. 21(a), a total wiring-to-substrate capacitance Cat corresponds to the sum of capacitances Ca1 and Ca2, which is represented by the following equation (1):
Cat=xcexa3Ca1+xcexa3Ca2xe2x80x83xe2x80x83(1).
In the case where a member interposed between the wiring and substrate is composed of a homogeneous material, the wiring-to-substrate capacitance per unit area is inversely proportional to the distance between the wiring and substrate, so that the capacitance is larger as the distance is shorter. If the total wiring-to-substrate of the semiconductor device shown in FIG. 21(b) is represented by Cbt when the dimension Da2 shown in FIG. 21(a) is equal to the dimension Dbt shown in FIG. 21(b), the following inequality (2) is satisfied:
Cat greater than Cbtxe2x80x83xe2x80x83(2),
which indicates that the wiring-to-substrate capacitance Cat in the structure shown in FIG. 21(a) is larger than the wiring-to-substrate capacitance Cbt in the structure shown in FIG. 21(b).
Although the formation of the island pattern composed of the dummy semiconductor portions in the isolation region has the advantage of achieving planarization with excellent in-plane uniformity, it also has the possibility of increasing the wiring-to-substrate capacitance and resultantly reducing the operating speed of the semiconductor device.
In view of the foregoing, the present invention has been achieved based on the principle that, if each electrode of a parallel-plate capacitor occupies an equal area, the capacitance of the capacitor is generally smaller as the distance between the electrodes is larger or on the physical phenomenon that, even when the capacitor has equal capacitance, the amount of charge accumulated therein is smaller as the voltage between the electrodes is lower.
It is therefore an object of the present invention to increase the operating speed of a trench-isolated semiconductor device comprising an isolation region consisting of trench portions and dummy semiconductor portions by providing therein means for reducing the wiring-to-substrate capacitance in the isolation region or means for reducing the amount of charge accumulated in the capacitance present between the wiring and substrate in the isolation region.
A first semiconductor device according to the present invention comprises: a semiconductor substrate having an active region and an isolation region surrounding the active region; a plurality of trench portions each formed in the isolation region and filled with an insulating material; semiconductor portions interposed between the individual trench portions in the isolation region; an interlayer insulating film formed to extend continuously over the active region and the isolation region; a wire formed on the interlayer insulating film; and at least one PN junction formed in the semiconductor portions underlying the wire.
In the arrangement, the capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions of the isolation region is obtained by adding in series the capacitance in the upper portion of the PN junction of each of the semiconductor portions to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film. Accordingly, the wiring-to-substrate capacitance of the whole semiconductor device is reduced, resulting in the semiconductor device operating at a higher speed.
The PN junction may include a plurality of PN junctions formed in the semiconductor portions.
The arrangement achieves a further reduction in wiring-to-substrate capacitance, resulting in a higher operating speed.
The active region may be formed with an impurity diffusion region and a PN junction may be formed at a bottom face of the impurity diffusion region, the PN junction of the isolation region being positioned at a level lower than the PN junction of the active region.
The arrangement further reduces the wiring-to-substrate capacitance.
A second semiconductor device according to the present invention comprises: a semiconductor substrate having an active region and an isolation region surrounding the active region; a plurality of trench portions each formed in the isolation region and filled with an insulating material; semiconductor portions interposed between the individual trench portions in the isolation region; an interlayer insulating film formed to extend continuously over the active region and the isolation region; a wire formed on the interlayer insulating film; and a dielectric film interposed between at least the semiconductor portions of the isolation region and the interlayer insulating film.
In the arrangement, the capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions of the isolation region is obtained by adding in series the capacitance in the dielectric film to the capacitance in the interlayer insulating film, so that the total wiring-to-substrate capacitance is lowered. Consequently, the operating speed of the semiconductor device is increased.
As the dielectric film, an underlying insulating film may be provided between the interlayer insulating film and the semiconductor portions and trench portions.
There can be further provided a gate electrode formed on the semiconductor substrate within the active region and sidewalls made of an insulating material and formed on both side faces of the gate electrode such that the underlying insulating film is formed of the same film as forming the sidewalls.
The underlying insulating film may be composed of a multilayer film.
The arrangement enables the underlying insulating film for reducing the wiring-to-substrate capacitance to be composed by using the sidewalls required to form a MOSFET of so-called LDD structure. Consequently, the wiring-to-substrate capacitance can be reduced, while avoiding an increase in manufacturing cost.
The dielectric film may be formed in an upper portion of each of the semiconductor portions of the semiconductor substrate to have a top face at approximately the same level as a top face of each of the trench portions.
Preferably, the dielectric film is composed of at least one of a silicon oxide film and a silicon nitride film.
A third semiconductor device according to the present invention comprises: a semiconductor substrate having an active region and an isolation region surrounding the active region; a plurality of trench portions each formed in the isolation region and filled with an insulating material; semiconductor portions interposed between the individual trench portions in the isolation region; an interlayer insulating film formed to extend continuously over the active region and the isolation region; a wire formed on the interlayer insulating film; and a buried insulating film formed in an inner portion of each of the semiconductor portions in the isolation region.
The arrangement allows a reduction in the wiring-to-substrate capacitance of the entire isolation region, resulting in a significant reduction in operating speed.
A fourth semiconductor device according to the present invention comprises: a semiconductor substrate having an active region and an isolation region surrounding the active region; a plurality of trench portions each formed in the isolation region and filled with an insulating material; semiconductor portions interposed between the individual trench portions in the isolation region; an interlayer insulating film formed to extend continuously over the active region and the isolation region; a wire formed on the interlayer insulating film; an a resistor film formed between the interlayer insulating film and at least the semiconductor portions of the isolation region.
In the arrangement, a voltage drop in the resistor film reduces the amount of charge accumulated in the wiring-to-substrate capacitance in the region of the semiconductor device containing the resistor film, though the wiring-to-substrate capacitance is not reduced in the region. Consequently, the time required for charging or discharging is reduced, resulting in the semiconductor device operating at a higher speed.
As the resistor film, an underlying resistor film may be formed to extend continuously over the semiconductor portions and trench portions.
The arrangement allows the wiring-to-substrate capacitance to be reduced by using various films having electric resistivity which are formed on the semiconductor substrate.
There can further be provided a resistor element formed on the semiconductor substrate and having a high resistor film such that the underlying resistor film is formed of the same film as composing the high resistor film of the resistor element.
In the arrangement, the underlying resistor film having the same resistance as the high resistor film used as a resistor element achieves a remarkable voltage dropping effect.
There can further be provided an element having an electrode member composed of a conductor film formed on the semiconductor substrate within the active region such that the resistor film is composed of the same material as composing the electrode member.
There can further be provided a FET having a gate electrode composed of a first conductor film formed on the semiconductor portion within the active region and a second conductor film deposited on the first conductor film such that a top surface of the first conductor film of the gate electrode is at approximately the same level as a top surface of each of the trench portions, while a region of the resistor film overlying each of the semiconductor portions is formed of the same two films as composing the first and second conductor films of the gate electrode and a region of the resistor film overlying each of the trench portions is composed of the same material as composing the first conductor film of the gate electrode.
Each of the arrangements eliminates the necessity for an additional step of forming the resistor film, so that the wiring-to-substrate capacitance is reduced, while an increase in manufacturing cost is prevented.
The resistor film may be formed in an upper portion of each of the semiconductor portions of the semiconductor substrate to have a top face at approximately the same level as a top surface of each of the trench portions.
The resistor film may be composed of a silicon film containing at least one of an oxygen atom and a nitrogen atom.
The resistor film may be composed of at least one of a polysilicon film and an amorphous silicon film.
The arrangement allows the formation of the resistor film by using the polysilicon film or amorphous silicon film to compose the gate electrode and the resistor element and thereby prevents an increase in manufacturing cost.
A first method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region of a first conductivity type, a first trench for partitioning the substrate region into an active region and an isolation region and a second trench for partitioning the isolation region into a plurality of dummy semiconductor portions; a second step of filling an insulating material in each of the first and second trenches to form a first buried trench portion and a second buried trench portion; a third step of forming an element on the active region; a fourth step of introducing an impurity containing at least an impurity of a second conductivity type into the dummy semiconductor portions of the isolation region to form at least one PN junction in the dummy semiconductor portions; a fifth step of forming an interlayer insulating film over an entire surface of the substrate; and a sixth step of forming a wire on the interlayer insulating film.
The methods enables the formation of the semiconductor device including the dummy semiconductor portions each having the PN junction. The capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions of the isolation region is obtained by adding in series the capacitance in the upper portion of the PN junction of each of the semiconductor portions to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film. Accordingly, the wiring-to-substrate capacitance of the whole semiconductor device is reduced, resulting in the semiconductor device operating at a higher speed.
The third and fourth steps may include forming a gate electrode of a FET as the element on the active region, introducing the impurity of the second conductivity type into the active region and the dummy semiconductor portions, and thereby forming source/drain regions of the FET, while forming the at least one PN junction in the dummy semiconductor portions.
The method enables the formation of the semiconductor device operating at a high speed by using a typical manufacturing process for forming a FET without an additional step of forming the PN junction in each of the dummy semiconductor portions.
The third step may include forming a gate electrode of a FET as the element on the active region by using a first mask covering the isolation region and introducing the impurity of the second conductivity type into the active region to form source/drain regions of the FET and the fourth step may include introducing the impurity containing at least the impurity of the second conductivity type into the dummy semiconductor portions by using a second mask covering the active region to form the at least one PN junction in the dummy semiconductor portions.
The method enables the formation of the semiconductor device having an arbitrary number of PN junctions without placing restraints on the depth and impurity concentration of the PN junction in the active region, resulting in a semiconductor device having minimum wiring-to-substrate capacitance.
A second method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region, a first trench for partitioning the substrate region into an active region and an isolation region and a second trench for partitioning the isolation region into a plurality of dummy semiconductor portions; a second step of filling an insulating material in each of the first and second trenches to form a first buried trench portion and a second buried trench portion; a third step of forming an element on the active region; a fourth step of forming a resistor film on each of the dummy semiconductor portions of the isolation region; a fifth step of forming an interlayer insulating film over an entire surface of the substrate; and a sixth step of forming a wire on the interlayer insulating film.
The method enables the formation of the semiconductor device comprising the resistor film between the interlayer insulating film and dummy semiconductor portions of the isolation region. A voltage drop in the resistor film reduces the amount of charge accumulated in the wiring-to-substrate capacitance, though the wiring-to-substrate capacitance is not reduced in the region containing the resistor film of the semiconductor device. Consequently, the time required for charging or discharging is reduced, resulting in the semiconductor device operating at a higher speed.
The fourth step may include composing the resistor film of a film containing at least one of polysilicon and amorphous silicon.
The fourth step may include composing the resistor film of a multilayer film constituted by two or more conductor films with at least an insulating film interposed therebetween.
The fourth step may include introducing an impurity at a concentration of 1xc3x971020 atomsxc2x7cmxe2x88x923 or lower into the resistor film.
A third method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region, a first trench for partitioning the substrate region into an active region and an isolation region and a second trench for partitioning the isolation region into a plurality of dummy semiconductor portions; a second step of filling an insulating material in each of the first and second trenches to form a first buried trench portion and a second buried trench portion; a third step of forming an element on the active region; a fourth step of implanting ions into an upper portion of each of the dummy semiconductor portions to form a high resistor portion therein; a fifth step of forming an interlayer insulating film over an entire surface of the substrate; and a sixth step of forming a wire on the interlayer insulating film.
The method allows the formation of the semiconductor device comprising the high resistor portion between the interlayer insulating film and dummy semiconductor portions of the isolation region. As described above, a voltage drop in the region containing the high resistor portion of the semiconductor device reduces the amount of charge accumulated in the wiring-to-substrate capacitance. What results is the semiconductor device which requires a shorter time for charging or discharging and therefore operates insulating film at a higher speed.
The fourth step may include implanting ions containing at least an atom having an oxidizing function to form the high resistor portion.
The fourth step may include implanting ions containing at least an atom having a nitriding function to form the high resistor portion.
A fourth method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region, a first trench for partitioning the substrate region into an active region and an isolation region and a second trench for partitioning the isolation region into a plurality of dummy semiconductor portions; a second step of filling an insulating material in each of the first and second trenches to form a first buried trench portion and a second buried trench portion; a third step of forming an element on the active region; a fourth step of forming an underlying insulating film over the dummy semiconductor portions of the isolation region; a fifth step of forming an interlayer insulating film over an entire surface of the substrate; and a sixth step of forming a wire on the interlayer insulating film.
In accordance with the method, there is formed the semiconductor device including the underlying insulating film beneath the interlayer insulating film in the isolation region thereof. Consequently, the capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions of the isolation region is obtained by adding in series the capacitance in the underlying insulating film to the capacitance in the interlayer insulating film, so that the total wiring-to-substrate capacitance is reduced. What results is the semiconductor device operating at a high speed.
The third step and the fourth step may include forming a gate electrode of a FET forming the element on the active region, depositing a dielectric film on the substrate, performing anisotropic etching with respect to the dielectric film by using a mask covering the isolation region, and thereby leaving sidewalls on both side faces of the gate electrode, while leaving the underlying insulating film over the dummy semiconductor portions.
The method enables the formation of a semiconductor device operating at a high speed by using a typical manufacturing process for forming a FET without an additional step of forming the underlying insulating film.
The fourth step may include forming the underlying insulating film of a dielectric film containing at least silicon oxide.
The fourth step may include forming the underlying insulating film of a dielectric film containing at least silicon nitride.
A fifth method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region, a first trench for partitioning the substrate region into an active region and an isolation region and a second trench for partitioning the isolation region into a plurality of dummy semiconductor portions; a second step of filling an insulating material in each of the first and second trenches to form a first buried trench portion and a second buried trench portion; a third step of forming an element on the active region; a fourth step of forming depressed portions by etching the dummy semiconductor portions and filling an insulating material in the depressed portions to form inter-trench insulating films each having a top face at the same level as respective top faces of the first and second buried trench portions; a fifth step of forming an interlayer insulating film over an entire surface of the substrate; and a sixth step of forming a wire on the interlayer insulating film.
In accordance with the method, there is formed the semiconductor device comprising the inter-trench insulating films between the interlayer insulating films and dummy semiconductor portions of the isolation region thereof. Consequently, the capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions of the isolation region is obtained by adding in series the capacitance in the inter-trench buried insulating films to the capacitance in the interlayer insulating film, so that the total wiring-to-substrate capacitance is reduced. What results is the semiconductor device operating at a high speed.
The fourth step may include forming each of the inter-trench insulating films of a dielectric film containing at least silicon oxide.
The fourth step may include forming each of the inter-trench insulating films of a dielectric film containing at least silicon nitride.
A sixth method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region, a first trench for partitioning the substrate region into an active region and an isolation region and a second trench for partitioning the isolation region into a plurality of dummy semiconductor portions; a second step of filling an insulating material in each of the first and second trenches to form a first buried trench portion and a second buried trench portion; a third step of forming an element on the active region; a fourth step of implanting oxygen ions into each of the dummy semiconductor portions to form a buried insulating film in an inner portion thereof; a fifth step of forming an interlayer insulating film over an entire surface of the substrate; and a sixth step of forming a wire on the interlayer insulating film.
A seventh method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region, a first trench for partitioning the substrate region into an active region and an isolation region and a second trench for partitioning the isolation region into a plurality of dummy semiconductor portions; a second step of filling an insulating material in each of the first and second trenches to form a first buried trench portion and a second buried trench portion; a third step of forming third trenches by etching the semiconductor portions and filling an insulating material in the third trenches to form buried insulating films each having a top face at a level lower than respective top faces of the first and second buried trench portions; a fourth step of growing semiconductor films on the buried insulating films, with the active region covered with a mask member, to form dummy semiconductor portions; a sixth step of forming an interlayer insulating film over an entire surface of the substrate; a fifth step of forming an element on the active region; a seventh step of forming a wire on the interlayer insulating film.
An eighth method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, in a semiconductor substrate having a substrate region, a first trench extending over an entire isolation region of the substrate region, while leaving an active region of the substrate region; a second step of filling an insulating material in the first trench to form a buried insulating film having a top face at the same level as a top face of the isolation region; a third step of growing a semiconductor film over the active region and the buried insulating film; a fourth step of forming, in the semiconductor substrate, a second trench for partitioning the semiconductor film and the substrate region into the active region and the isolation region and a third trench for partitioning the portion of the semiconductor film overlying the isolation region into a plurality of dummy semiconductor portions; a fifth step of filling an insulating material in each of the second and third trenches to form a first buried trench portion and a second buried trench portion; a sixth step of forming an element on the portion of the semiconductor film overlying the active region; a seventh step of forming an interlayer insulating film over an entire surface of the substrate; and an eighth step of forming a wire on the interlayer insulating film.
In accordance with the methods, there are obtained semiconductor devices each comprising a buried insulating film at a depth of each of the dummy semiconductor portions of the isolation region. What results is the semiconductor device having smaller wiring-to-substrate capacitance and operating at a higher speed.